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- **2026 Revenue Growth Catalyst**: CEO confident SRH FPGA storefront revenue will contribute 10%+ of total 2026 revenue, driven by DIB demand for strategic rad-hard solutions.
- **Q4 Revenue Risk**: $3M commercial contract timing creates wide guidance range ($3.5M-$6M), with 68% gross margin if fully recognized in Q4.
- **Government Shutdown Resilience**: No program cancellations; company prepared with $2M ATM funding to offset potential payment delays.
- **12LP Process Dominance**: QuickLogic's eFPGA Hard IP uniquely positions for U.S.-fabricated ASICs, addressing $500M+ DIB semiconductor TAM.

**【CEO Opening Remarks】**
- CEO Brian Faith highlighted significant progress since Q2, including engineering team achievements in securing design wins for Radot FPGA and high-density eFPGA Hard IP.
- Q4 revenue guidance of $3.5M-$6M, driven by a potential $3M commercial contract for advanced fabrication node designs.
- Emphasized accelerating storefront revenue in 2026, with SRH FPGA test chip delivery expected in Q1 2026 and dev kits for DIBs by late Q4.
- Noted expanding commercial market penetration, with license revenue potentially surpassing NRE revenue in Q3.

**【CFO Financial Commentary】**
- Q3 2025 revenue: $2M (down 52.5% YoY, $1M new product, $1.1M mature product).
- Non-GAAP net loss: $3.2M ($0.19 per share), driven by lower gross margin (-11.9%) due to fixed cost absorption and R&D allocation.
- Q4 guidance: $3.5M-$6M revenue, with gross margin 45%-68% depending on contract timing.
- Cash position: $17.3M (including $15M credit facility utilization), with $1.9M cash usage in Q3 for test chip fabrication.

**【Q&A Highlights】**
- **Government Shutdown Impact**: CFO Elias Nader stated no cancellations, but delays in U.S. government contract payments could affect Q4 cash flow. Company prepared with $2M ATM funding.
- **Storefront Revenue Potential**: CEO expects 10%+ of total 2026 revenue from SRH FPGA storefront sales, driven by DIB demand for strategic rad-hard solutions.
- **FPGA vs. ASIC Dynamics**: 12LP process dominates DIB ASIC development due to U.S. fabrication requirements; QuickLogic's eFPGA Hard IP offers flexibility for both ASIC and discrete FPGA designs.
- **Spending Plans**: CFO projects Q4 OpEx ~$3M, with potential hires in engineering and FAE to support growing customer pipeline.
- **Contract Timing Risk**: CEO acknowledged $3M contract could slip to Q1 2026, reducing Q4 revenue to $3.5M.


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