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- **2026 Revenue Growth Catalyst**: CEO confident SRH FPGA storefront revenue will contribute 10%+ of total 2026 revenue, driven by DIB demand for strategic rad-hard solutions.
- **Q4 Revenue Risk**: $3M commercial contract timing creates wide guidance range ($3.5M-$6M), with 68% gross margin if fully recognized in Q4.
- **Government Shutdown Resilience**: No program cancellations; company prepared with $2M ATM funding to offset potential payment delays.
- **12LP Process Dominance**: QuickLogic's eFPGA Hard IP uniquely positions for U.S.-fabricated ASICs, addressing $500M+ DIB semiconductor TAM.

**【CEO Opening Remarks】**
- CEO Brian Faith highlighted significant progress since Q2, including engineering team achievements in securing design wins for Radot FPGA and high-density eFPGA Hard IP.
- Q4 revenue guidance of $3.5M-$6M, driven by a potential $3M commercial contract for advanced fabrication node designs.
- Emphasized accelerating storefront revenue in 2026, with SRH FPGA test chip delivery expected in Q1 2026 and dev kits for DIBs by late Q4.
- Noted expanding commercial market penetration, with license revenue potentially surpassing NRE revenue in Q3.

**【CFO Financial Commentary】**
- Q3 2025 revenue: $2M (down 52.5% YoY, $1M new product, $1.1M mature product).
- Non-GAAP net loss: $3.2M ($0.19 per share), driven by lower gross margin (-11.9%) due to fixed cost absorption and R&D allocation.
- Q4 guidance: $3.5M-$6M revenue, with gross margin 45%-68% depending on contract timing.
- Cash position: $17.3M (including $15M credit facility utilization), with $1.9M cash usage in Q3 for test chip fabrication.

**【Q&A Highlights】**
- **Government Shutdown Impact**: CFO Elias Nader stated no cancellations, but delays in U.S. government contract payments could affect Q4 cash flow. Company prepared with $2M ATM funding.
- **Storefront Revenue Potential**: CEO expects 10%+ of total 2026 revenue from SRH FPGA storefront sales, driven by DIB demand for strategic rad-hard solutions.
- **FPGA vs. ASIC Dynamics**: 12LP process dominates DIB ASIC development due to U.S. fabrication requirements; QuickLogic's eFPGA Hard IP offers flexibility for both ASIC and discrete FPGA designs.
- **Spending Plans**: CFO projects Q4 OpEx ~$3M, with potential hires in engineering and FAE to support growing customer pipeline.
- **Contract Timing Risk**: CEO acknowledged $3M contract could slip to Q1 2026, reducing Q4 revenue to $3.5M.


QuickLogic Corporation (QUIK) Q3 2025 Earnings Call Transcript

- **Strategic FPGA Push**: $3.7M Q2 revenue reflects delayed Q3 revenue to prioritize SRH FPGA test chip and Australis 2.0, targeting Q4 surge. Defense-focused SRH FPGA test chip on 12LP node positions for multi-million dollar contracts in 2026.
- **Performance Improvements**: Australis 2.0 with Synplify integration delivers 35% max frequency and 50% resource utilization gains. Digital proof-of-concept chiplet to accelerate storefront adoption.
- **Defense Market Growth**: U.S. defense spending on onshore semiconductors drives FPGA/ASIC demand (~$5B annually). Test chips expected to generate 2026 revenue, with potential 2027 volume sales.
- **Financial Outlook**: Q3 revenue $2M (±10%), Q4 rebound. Full-year 2025 revenue modestly lower than 2024, with non-GAAP gross margin in low-to-mid 50% range.

**【CEO Summary Section】**
- **Strategic FPGA Investments**: Accelerated engineering resources toward two initiatives—SRH FPGA test chip and Australis 2.0—delaying Q3 revenue recognition but positioning for Q4 surge. SRH FPGA test chip, developed on GlobalFoundries' 12LP node, targets defense programs requiring U.S.-fabricated, rad-hard devices. Expected ROI from 2026, with potential multi-million dollar storefront contracts.
- **Australis 2.0 Update**: First eFPGA IP using 2.0 tools for a 12nm contract to be delivered in Q4, supporting high-density designs. Integration with Synopsys Synplify tool improves performance by 35% and resource utilization by 50%.
- **Digital Proof-of-Concept Chiplet**: Low-cost, customizable chiplet for advanced nodes, designed as a storefront device with third-party IP, to be completed pre-next call.
- **Government Contract Update**: Q3 revenue from U.S. government SRH FPGA contract minimal due to subcontractor delays, rebounding in Q4.
- **Board Changes**: Christine Russell's passing and Ron Shelton's appointment as Audit Chair, leveraging his semiconductor and financial expertise.

**【CFO Financial Commentary】**
- **Q2 2025 Results**: Total revenue $3.7M (-10.7% YoY), non-GAAP net loss $1.5M. New product revenue $2.9M (-4.5% YoY). Non-GAAP gross margin 31% (down from 54.4% YoY) due to COGS allocations and lower revenue.
- **Q3 Guidance**: Revenue $2M (±10%), non-GAAP gross margin ~5% due to lower absorption. Q4 expected to rebound, with full-year 2025 revenue modestly lower than 2024.
- **Cash Position**: $19.2M at Q2 close, including $15M credit facility usage. Q2 cash usage $1.3M, with $2.9M raised via ATM for strategic initiatives.

**【Q&A Key Highlights】**
- **Defense Market Momentum**: CEO confident in SRH FPGA test chip's ability to secure design wins in 2026, driven by U.S. defense spending on onshore-manufactured semiconductors. FPGA and ASIC categories represent ~50% of DIB semiconductor TAM.
- **Competitive Differentiation**: Unique positioning with rad-hard FPGAs on 12LP node, no direct competitors in this space. Test chips expected to generate revenue in 2026, with potential for volume sales in 2027.
- **Australis 2.0 Impact**: Accelerated development to handle high-density designs, enabling parallel customer engagements. Customers expanding requirements due to tool's capabilities.
- **Financial Outlook**: CFO emphasizes Q4 revenue surge, with Q3 as trough. Full-year 2025 non-GAAP gross margin expected in low-to-mid 50% range, driven by higher Q4 revenue.

QuickLogic Corporation (QUIK) Q2 2025 Earnings Call Transcript

- **Intel 18A Leadership**: Delivered first eFPGA Hard IP for Intel 18A test chip, positioning QuickLogic as sole provider for defense and commercial ASIC integration. Q2 revenue delayed to $4M, but full-year growth intact.
- **Defense Contract Expansion**: $6.6M Rad-Hard FPGA contract with incremental funding, plus first direct-to-storefront defense deal. Storefront model gains traction for recurring revenue.
- **Commercial Breakthrough**: Faraday partnership targets $1.5B FPGA market with 22nm eFPGA-integrated SoC, with H2 2025 license revenue and long-term royalties.
- **Financial Resilience**: Q1 non-GAAP loss $1.1M, but $17.6M cash cushion supports Intel 18A investments. Full-year targets: profitability, positive cash flow, and solid growth.

**【CEO Key Highlights】**
- **Intel 18A Momentum**: Delivered design-specific eFPGA Hard IP for a customer's Intel 18A test chip, with potential revenue recognition delayed to Q4 2025 due to funding delays. Q2 revenue guidance is $4 million, but full-year outlook remains solid for growth and profitability.
- **Defense Contracts**: Secured a $6.6 million Strategic Radiation-Hardened FPGA contract with incremental funding, targeting space and strategic applications. Direct-to-storefront opportunities are emerging, with first phase of a new defense contract completed.
- **Commercial Expansion**: Collaborated with Faraday on a 22nm eFPGA-integrated SoC platform, targeting low-power IoT and industrial applications. This partnership highlights the potential for IP license and royalty revenue starting H2 2025.

**【CFO Financial Overview】**
- **Q1 2025 Results**: Total revenue $4.3 million (down 28% YoY), driven by new product shipments. Non-GAAP net loss $1.1 million (-$0.07 per share), impacted by COGS allocation and lower gross margin (45.7%).
- **Q2 Guidance**: Revenue $4 million (±10%), with non-GAAP gross margin ~50% and net loss $1.1-1.2 million. Full-year target: solid growth, non-GAAP profitability, and positive cash flow.
- **Cash Position**: $17.6 million (including $15M credit facility), supporting investments in Intel 18A IP development and AuroraPro tool integration.

**【Q&A Key Takeaways】**
- **Intel 18A Pipeline**: Multiple design engagements across defense and commercial markets, with test chips entering fabrication. Royalty opportunities expected post-2025 as customers transition to production.
- **Storefront Growth**: First direct-to-storefront contract booked, with potential for additional storefront revenue from defense and commercial customers. Faraday partnership exemplifies the storefront model's scalability.
- **Rad-Hard Outlook**: Strategic FPGA contract progressing with subcontractor delays, but long-term potential for high-margin, recurring revenue.


QuickLogic (QUIK)-13 May 25-2025 Q1 Earnings call transcript

- **Q2 2025 Revenue Surge**: >$6M from Intel 18A and DIB contracts, enabling non-GAAP profitability.
- **Intel 18A Dominance**: Only company with eFPGA Hard IP for Intel 18A, targeting mid-seven figures in Q2.
- **AI & Chiplet Growth**: Low-power AI inferencing and ASIC Chiplets (e.g., YorChip) driving edge computing opportunities.
- **Cash Flow Confidence**: $21.9M cash and $18M credit facility support 2025 expansion, with Q2+ positive cash flow.
- **Market Diversification**: Expanding beyond DIB into industrial, communications, and consumer markets while maintaining >50% DIB revenue.

**【CEO Key Highlights】**
- **Q4 2024 Revenue & Contracts**: Reported $5.7M revenue, below midpoint of guidance due to delayed contract awards. Secured two new eFPGA Hard IP contracts ($1.1M and mid-seven figures) and expects Q2 2025 revenue rebound to >$6M.
- **Intel 18A Opportunity**: Only company with eFPGA Hard IP optimized for Intel 18A. Anticipates mid-seven figures in Q2 2025 from two pending contracts, leveraging $18M credit facility for development.
- **Market Expansion**: Diversifying into industrial, communications, and consumer markets while maintaining >50% defense industrial base (DIB) revenue. New VP of Sales (ex-FlexLogix) is converting FlexLogix customers to QuickLogic.
- **AI & Chiplet Growth**: Edge AI inferencing applications (e.g., low-power processing with ETH Zurich) and ASIC Chiplet solutions (e.g., YorChip Merchant Chiplets) are key growth areas.
- **Long-Term Leverage**: Reusing established eFPGA Hard IP for 12LP, 22FDX, and UMC 22nm processes reduces development costs and accelerates revenue recognition.

**【CFO Financial Summary】**
- **Q4 2024 Results**: 
  - Total revenue: $5.7M (down 24% YoY, +34% QoQ)
  - Non-GAAP gross margin: 62% (vs. 78.3% YoY, 60% QoQ)
  - Non-GAAP net income: $0.6M ($0.04 EPS)
  - Cash: $21.9M (incl. $18M credit facility)
- **Q1 2025 Guidance**: 
  - Revenue: ~$4M (±10%), with 85% from new products
  - Non-GAAP gross margin: ~50% (due to lower revenue)
  - Non-GAAP net loss: $1.2M-$1.4M
- **2025 Outlook**: Solid revenue growth, non-GAAP profitability, and positive cash flow driven by Intel 18A and Direct to Storefront contracts.

**【Q&A Key Takeaways】**
- **Q2 2025 Revenue**: Expected >$6M from Intel 18A and DIB contracts, enabling non-GAAP profitability.
- **Distributor Impact**: EOS S3 shipments growing sequentially, with distributors targeting new designs for 2026+.
- **AI Inferencing**: Customer using eFPGA for ultra-low-power AI processing in IoT devices, with potential 20x energy savings vs. RISC-V alone.
- **Government Contracts**: Strategic Rad-Hard FPGA program total potential $72M, with Q4 2024 tranche bringing total to $34M.
- **Direct to Storefront**: New DIB contract for low-power algorithm processing, with Storefront revenue potential starting 2027.

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