Microchip Introduces Switchtec Gen 6 PCIe Switches for AI Workloads and HPC Applications.

Microchip Technology has introduced its next generation of Switchtec Gen 6 PCIe Switches, the industry's first manufactured using a 3nm process. The switches offer lower power consumption and support up to 160 lanes for high-density AI system connectivity. They also feature advanced security features, including hardware root of trust and secure boot, utilizing post-quantum safe cryptography compliant with CNSA 2.0. The switches aim to address bandwidth bottlenecks in previous PCIe generations, doubling the bandwidth to 64 GT/s.

Microchip Technology (Nasdaq: MCHP) has introduced its next generation of Switchtec Gen 6 PCIe Switches, marking a significant milestone in the industry. These switches are the first to be manufactured using a 3nm process, offering lower power consumption and support for up to 160 lanes for high-density AI system connectivity. The new switches also incorporate advanced security features, including hardware root of trust and secure boot, utilizing post-quantum safe cryptography compliant with CNSA 2.0 Microchip Unveils First 3 nm PCIe® Gen 6 Switch to Power Modern AI Infrastructure^[1].

The Switchtec Gen 6 PCIe switches aim to address the bandwidth bottlenecks experienced in previous PCIe generations. By doubling the bandwidth to 64 GT/s (giga transfers per second) per lane, these switches provide the necessary data pipeline to keep the most powerful AI accelerators consistently supplied. This increased bandwidth is crucial for high-performance computing (HPC) applications and cloud computing, which are driving unprecedented demand for faster data movement and lower latency Microchip Unveils First 3 nm PCIe® Gen 6 Switch to Power Modern AI Infrastructure^[1].

The new switches feature 20 ports and 10 stacks, with each port equipped with hot- and surprise-plug controllers. They support NTB (Non-Transparent Bridging) to connect and isolate multiple host domains and multicast for one-to-many data distribution within a single domain. The switches also incorporate advanced error containment and comprehensive diagnostics and debug capabilities, along with a wide breadth of I/O interfaces and an integrated MIPS processor with bifurcation options at x8 and x16 Microchip Unveils First 3 nm PCIe® Gen 6 Switch to Power Modern AI Infrastructure^[1].

The Switchtec Gen 6 PCIe switches are designed to facilitate direct communication between critical compute resources, which is essential for reducing signal loss and maintaining the low latency required by AI fabrics. The PCIe 6.0 standard introduces Flow Control Unit (FLIT) mode, a lightweight Forward Error Correction (FEC) system, and dynamic resource allocation, making data transfer more efficient and reliable, especially for small packets common in AI workloads Microchip Unveils First 3 nm PCIe® Gen 6 Switch to Power Modern AI Infrastructure^[1].

Development tools, such as Microchip’s ChipLink diagnostic tools, support the Switchtec Gen 6 PCIe Switch family, offering comprehensive debug, diagnostics, configuration, and analysis through an intuitive graphical user interface (GUI). The switches are also supported by the PM61160-KIT Switchtec Gen 6 PCIe Switch Evaluation Kit with multiple interfaces Microchip Unveils First 3 nm PCIe® Gen 6 Switch to Power Modern AI Infrastructure^[1].

Microchip Technology's commitment to innovation is evident in this latest product line, which aims to enable the transformation of data center architectures. By expanding the proven Switchtec product line to PCIe 6.0, Microchip is facilitating direct communication between critical compute resources and delivering the most powerful and energy-efficient switch to date Microchip Unveils First 3 nm PCIe® Gen 6 Switch to Power Modern AI Infrastructure^[1].