Cadence and TSMC Collaborate on Advanced Chip Design Automation and IP for Next-Generation AI and HPC Applications

Cadence has partnered with TSMC to develop advanced design infrastructure and accelerate time to market for AI and HPC applications. The partnership has led to advancements in chip design automation and IP, including AI-driven EDA, 3D-ICs, and photonics. Cadence has collaborated with TSMC on design infrastructure for advanced process nodes, including N3, N2, and A16, using various Cadence tools and solutions. Several new Cadence IP are now silicon-proven and available for TSMC N3P. The partnership aims to speed up and improve the design process for advanced silicon for customers.

Cadence Design Systems, Inc. (NASDAQ: CDNS) and Taiwan Semiconductor Manufacturing Company (TSMC) have recently announced a significant advancement in their long-standing partnership, which is aimed at developing advanced design infrastructure and accelerating time to market for AI and high-performance computing (HPC) applications. This collaboration has led to substantial progress in chip design automation and IP, including AI-driven electronic design automation (EDA), 3D integrated circuits (3D-ICs), and photonics.

The partnership has focused on several key areas, including design infrastructure for advanced process nodes such as TSMC's N3, N2, and A16. Cadence has utilized its suite of tools and solutions, including the CadenceInnovusImplementation System, Quantus Extraction Solution, Tempus Timing Solution, and ECO Option, among others. These tools have enabled the development of AI-driven design flows for chip and 3D-IC designs using TSMC's advanced process technologies.

One of the notable outcomes of this collaboration is the availability of several new Cadence IP solutions that are now silicon-proven and ready for TSMC's N3P process technology. These IP solutions include the first high-bandwidth memory (HBM4) IP at N3P, high-speed memory interfaces like LPDDR6/5X at 14.4G, and versatile DDR5 12.8G MRDIMM Gen2 IP. Additionally, Cadence has led the development of connectivity solutions such as PCI Express (PCIe) 7.0 IP and the first eUSB2V2 and Universal Chiplet Interconnect (UCIe) 32G IP, which support emerging AI PC and chiplet ecosystems.

The partnership aims to enhance design performance and energy efficiency for AI and HPC systems by streamlining the customer journey from design to silicon. Cadence and TSMC, along with the Open Innovation Platform (OIP) ecosystem, are collectively empowering the AI supercycle by addressing intricate challenges in semiconductor development.