Cadence's Trading Volume Surges 42.15% to $509 Million, Securing 199th Position in Daily Rankings

On June 16, 2025, Cadence's trading volume reached $509 million, marking a 42.15% increase from the previous day. This surge placed Cadence at the 199th position in terms of trading volume for the day.

Cadence has expanded its collaboration with Samsung Foundry, introducing a new multi-year IP agreement and joint development initiatives. This partnership aims to advance AI-driven design solutions for Samsung's SF4X, SF5A, and SF2P process nodes, targeting applications in AI data centers, automotive (including ADAS), and RF connectivity. Key developments include expanded memory and interface IP solutions, digital full flow certification for the SF2P node, automated analog design migration from 4nm to 2nm, RF chip/package co-design capabilities, and enhanced 3D-IC power integrity analysis. The collaboration has achieved significant milestones, including resolving 80-90% of IR-drop violations in high-speed CPU chips and streamlining design processes for mmWave applications. The partnership aims to accelerate the time to market for SoCs, chiplets, and 3D-ICs while enhancing designer productivity.

Cadence has also announced its collaboration with NVIDIA to provide optimized solutions for the world's first industrial AI cloud. This partnership enables European manufacturers to access Cadence's design tools optimized for NVIDIA Grace Blackwell platforms, including the Fidelity CFD Platform, Spectre X Simulator, Voltus IC Power Integrity Solution, and Innovus Implementation System. The solutions, running on NVIDIA's infrastructure of 10,000 Blackwell GPUs, offer up to 80X acceleration in solver performance. A notable success case is Ascendance, which achieved 20X faster simulation runtimes in aviation design. The collaboration also features the NVIDIA Omniverse Blueprint integration with Cadence Reality Digital Twin Platform for optimized AI factory operations. Additionally, Cadence introduced its Millennium M2000 Supercomputer, combining their software with NVIDIA CUDA-X libraries and Blackwell platform to accelerate silicon, system, and drug design workflows.

Cadence has unveiled the Tensilica NeuroEdge 130 AI Co-Processor (AICP), a new processor designed to complement neural processing units (NPUs) for AI applications. The processor delivers 30% area savings and over 20% reduction in dynamic power and energy while maintaining performance levels. The NeuroEdge 130 AICP features an extensible design compatible with various NPUs and is supported by the NeuroWeave Software Development Kit. The processor is specifically designed for end-to-end execution of agentic and physical AI networks in automotive, consumer, industrial, and mobile SoCs. It includes VLIW-based SIMD architecture with configurable options and optimized ISA for non-NPU tasks. The product is currently available and is ISO 26262-ready for automotive applications.

Cadence has significantly expanded its design IP portfolio optimized for Intel 18A and Intel 18A-P technologies, focusing on advancing AI, HPC, and mobility applications. The collaboration includes new IP additions such as 224G SerDes, DDR5-12.8G, and UCIe 1.1 48G for chiplet architectures. AI-driven digital and analog/custom design solutions certified for Intel 18A PDK and advanced packaging workflow development using Intel's EMIB-T technology are also part of the expansion. As a founding member of the Intel Foundry Chiplet Alliance, Cadence is strengthening its partnership with Intel Foundry to deliver optimized power, performance, and area efficiencies. The expanded portfolio leverages RibbonFET Gate-all-around transistors and PowerVia backside power delivery network, enabling customers to accelerate time-to-market for cutting-edge system-on-chip designs.

Cadence has strengthened its partnership with TSMC to accelerate 3D-IC and advanced-node technology development through certified design flows and silicon-proven IP. The collaboration includes certification for TSMC's N2P and A16 technologies, with initial work on A14 technology. Key developments include TSMC9000 pre-silicon-certified DDR5 12.8G IP for N2P, certified IP for TSMC's N5A and N3A processes targeting automotive applications, and expansion of design IP portfolio with HBM3E 9.6G in N5/N4P and pre-silicon HBM3E 10.4G in N3P. The partnership focuses on AI chip design innovation, automotive solutions for ADAS and autonomous driving, and advancement in 3DFabric solutions for chiplet design and packaging.

Cadence has unveiled the industry's first DDR5 12.8Gbps MRDIMM Gen2 memory IP system solution on TSMC N3 process, targeting enterprise and data center applications with AI processing demands. The solution features a doubled bandwidth compared to current DDR5 6400Mbps DRAM parts. The new memory IP system includes a PHY and high-performance controller, offering ultra-low latency encryption and advanced RAS features. The solution has been validated in hardware using the latest Gen2 MRDIMMs and is designed to enable advanced SoCs and chiplets with flexible floorplan options. The technology has already secured multiple engagements with leading AI, HPC, and data center customers. The solution is compatible with Micron's 1γ-based DRAM and Montage's MRCD02/MDB02 chips for MRDIMMs, positioning it as a key enabler for next-generation server and data center products.