Cadence and NVIDIA Collaborate to Achieve Billion-Gate AI Design Power Analysis

Cadence and NVIDIA have collaborated to develop a technology for power analysis of billion-gate AI designs, achieving a significant leap forward in the field. The Cadence Palladium Z3 Enterprise Emulation Platform, utilizing the Dynamic Power Analysis (DPA) App, can now accurately estimate power consumption under real-world workloads, allowing for efficient silicon and system designs. This innovation enables designers to confidently meet performance and power targets, accelerating their time to market.

Cadence (Nasdaq: CDNS) and NVIDIA have collaboratively developed a groundbreaking technology for power analysis of billion-gate AI designs. This innovation leverages the Cadence Palladium Z3 Enterprise Emulation Platform, enhanced by the Dynamic Power Analysis (DPA) App. The new technology can accurately estimate power consumption under real-world workloads, enabling more efficient silicon and system designs [1].

The collaboration allows for significant advancements in the power analysis of pre-silicon designs, processing billions of cycles in as few as two to three hours with up to 97 percent accuracy [1]. This breakthrough is particularly beneficial for semiconductor and systems developers targeting AI, machine learning (ML), and GPU-accelerated applications, as it enables them to design more energy-efficient systems and accelerate their time to market.

The Palladium Z3 Platform, with the DPA App, can verify functionality, power usage, and performance before tapeout, when the design can still be optimized. This is especially useful in AI, ML, and GPU-accelerated applications, where early power modeling increases energy efficiency and avoids delays from over- or under-designed semiconductors [1].

Cadence and NVIDIA’s collaboration has redefined the boundaries of what is possible in power analysis, empowering customers to confidently meet aggressive performance and power targets and accelerate their time to silicon [1]. This technology is integrated into the Cadence analysis and implementation solution, addressing power estimation, reduction, and signoff throughout the entire design process.

For more information, please visit the Cadence Palladium web page.

References:
[1] https://www.businesswire.com/news/home/20250813670044/en/Cadence-Accelerates-Development-of-Billion-Gate-AI-Designs-with-Innovative-Power-Analysis-Technology-Built-on-NVIDIA