Accelerating Failure Analysis of Heterogeneously Integrated Packages with AI-Powered Correlative Microscopy: A New Workflow for Next-Generation Packages

This article discusses the challenges of failure analysis in heterogeneously integrated packages, particularly in hybrid bonding and fan-out wafer-level packaging (FOWLP). The authors propose an AI-powered correlative microscopic workflow to map defective sites and surrounding structures. The workflow combines non-destructive X-ray microscopy, FIB polishing, and high-resolution SEM. The deep learning-based reconstruction method accelerates data acquisition. The article provides application examples of next-generation packages, demonstrating the performance and efficiency of the proposed workflow.

In the rapidly evolving landscape of semiconductor innovation, failure analysis in heterogeneously integrated packages, particularly in hybrid bonding and fan-out wafer-level packaging (FOWLP), has become increasingly challenging. Traditional methods often fall short in identifying and mapping defective sites and surrounding structures. However, a new AI-powered correlative microscopic workflow is emerging as a promising solution. This workflow combines non-destructive X-ray microscopy, FIB polishing, and high-resolution SEM, with a deep learning-based reconstruction method that accelerates data acquisition [1].

The proposed workflow begins with non-destructive X-ray microscopy, which provides a comprehensive view of the package without damaging the structure. This is followed by FIB polishing, which refines the surface for high-resolution SEM imaging. The high-resolution SEM then captures detailed images of the defective sites and their surrounding structures. The deep learning-based reconstruction method then processes this data, providing a comprehensive and accelerated analysis of the package [2].

This AI-powered approach has significant applications in next-generation packages. For instance, NVIDIA’s H100 and AMD’s MI300 use advanced packaging to accommodate massive memory bandwidth, heat dissipation, and parallelism. The proposed workflow can identify and rectify potential failure points in these high-performance chips, ensuring optimal performance and longevity [3].

Moreover, the workflow’s efficiency and accuracy make it particularly valuable for automotive and radar systems. Advanced driver-assistance systems (ADAS) and radar chips require thermal resilience and reliability. The proposed workflow can help identify and address thermal bottlenecks and other defects, ensuring these systems perform reliably under varying conditions [4].

In the smartphone and wearable device market, compact form factors and performance needs are pushing the adoption of FOWLP and SIPs (System in Package). The proposed workflow can enhance the reliability of these packages, ensuring they meet the demanding performance requirements of modern devices [5].

The semiconductor industry is at the forefront of innovation, and the proposed workflow represents a significant step forward in failure analysis. As the industry continues to push the bounds of capability, the ability to accurately and efficiently identify and rectify defects will be crucial. The companies that invest in and adopt this technology will be well-positioned to lead the next generation of semiconductor innovation.

References:
1. [1] https://www.bisinfotech.com/why-chip-packaging-is-the-new-battleground-for-semiconductor-innovation/
2. [2] https://www.bisinfotech.com/why-chip-packaging-is-the-new-battleground-for-semiconductor-innovation/
3. [3] https://www.bisinfotech.com/why-chip-packaging-is-the-new-battleground-for-semiconductor-innovation/
4. [4] https://www.bisinfotech.com/why-chip-packaging-is-the-new-battleground-for-semiconductor-innovation/
5. [5] https://www.bisinfotech.com/why-chip-packaging-is-the-new-battleground-for-semiconductor-innovation/